Method of programming nonvolatile memory device

ABSTRACT

A method of programming a nonvolatile memory device includes sequentially programming first to (n−1) th  logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n−1) th  logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n−1) th  latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n−1) th  logical pages, and latching new program data, received along with the second program command, in an n th  latch of the corresponding page buffer and programming the data, stored in the first to n th  latches of the page buffer, into a first physical page of a second memory block of the memory blocks.

CROSS-REFERENCE TO RELATED APPLICATION

Priority to Korean patent application number 10-2009-0008801 filed onFeb. 4, 2009, the entire disclosure of which is incorporated byreference herein, is claimed.

BACKGROUND

One or more embodiments relate to a method of programming a nonvolatilememory device and, more particularly, to a method of programming anonvolatile memory device, which is capable of storing 3-bitinformation.

A nonvolatile memory device has the advantages of random access memory(RAM), which enables the writing and erasure of data, and read onlymemory (ROM), which retains data even without the supply of power, andso has recently been widely used for the storage media of portableelectronic devices, such as digital cameras, personal digital assistants(PDAs), and MP3 players.

The nonvolatile memory device includes a memory cell array, a rowdecoder, a page buffer unit, etc. The memory cell array includes aplurality of word lines elongated in rows, a plurality of bit lineselongated in columns, and a plurality of cell strings corresponding tothe respective bit lines.

Memory cells have varying threshold voltages according to their programstates. It is ideal that the memory cells have the same thresholdvoltage according to the state of data to be stored. However, in thecase in which a program operation is actually performed on the memorycells, the threshold voltages of the memory cells have a differentprobability distribution in each region because of various externalenvironments, such as the device characteristics and the couplingeffect.

To increase the amount of data to be stored, a multi-level cell (MLC)capable of storing data of 2 bits or more in one memory cell wasdeveloped.

To store data of 2 bits or more in a memory cell, the number ofthreshold voltage distributions of the MLC is many and the time that ittakes to perform a program operation in the MLC is long, as comparedwith a single level cell (SLC) capable of storing only one bitinformation.

Unlike in the SLC in which a program operation is performed using oneword line as one page, in the MLC, a program operation is performedusing many logical pages on the assumption that the MLC has the numberof logical pages equal to the number of bits that can be stored inrelation to one word line.

For example, an MLC capable of storing 2-bit information logicallyincludes a least significant bit (SLC) page and a most significant bit(MSB) page in relation to one word line (i.e., a physical page). An MLCcapable of storing 3-bit information logically includes an LSB page, acenter significant bit (CSB) page, and an MSB page in relation to oneword line.

Accordingly, while the logical pages are programmed, neighboring memorycells are continuously subject to interference, which leads to a failurein an ideal threshold voltage distribution.

BRIEF SUMMARY

One or more embodiments relate to a method of programming a nonvolatilememory device, which is capable of minimizing the effect of interferenceon neighboring cells while program operations are performed in anonvolatile memory device having MLCs.

A method of programming a nonvolatile memory device according to anembodiment of this disclosure includes a step of providing a number ofmemory blocks each configured to comprise a number of physical pages,each of which has an n number of logical pages, where n is a positiveinteger, and providing a number of page buffers commonly coupled to thememory blocks, a first program step of sequentially programming first to(n−1)^(th) logical pages of all the physical pages of a first memoryblock of the memory blocks in response to a first program command, astep of loading data of the first to (n−1)^(th) logical pages stored ina first physical page of the first memory block and latching the loadeddata in first to (n−1)^(th) latches of each of the page buffers,respectively, when receiving a second program command after programmingall the first to (n−1)^(th) logical pages, and a second program step oflatching new program data, received along with the second programcommand, in an n^(th) latch of the corresponding page buffer andprogramming the data, stored in the first to n^(th) latches of the pagebuffer, into a first physical page of a second memory block of thememory blocks.

The method further includes a step of resetting all the latches of thepage buffer, loading data of first to (n−1)^(th) logical pages of asecond physical page of the first memory block, and latching the loadeddata in the first to (n−1)^(th) latches of the page buffer,respectively, when receiving a third program command after completingthe second program step, and a third program step of latching newprogram data, received along with the third program command, in then^(th) latch of the page buffer and programming the data, stored in thefirst to n^(th) latches of the page buffer, into a second physical pageof the second memory block.

The method further includes the step of erasing the first memory block,after data of first to (n−1)^(th) logical pages, stored in all thephysical pages of the first memory block, are programmed into the secondmemory block.

The method further comprises the steps of selecting the first memoryblock or a third memory block of the number of the memory blocks andprogramming first to (n−1)^(th) logical pages of all physical pages ofthe first memory block or the third memory block, after erasing thefirst memory block, and loading data stored in the first memory block orthe third memory block and programming the loaded data, together withnew program data, into a fourth memory block of the number of the memoryblocks.

A method of programming a nonvolatile memory device includes a step ofproviding an N number of memory blocks, where N is a positive integer,each configured to comprise physical pages each including an m number oflogical pages, where m is a positive integer, and providing a number ofpage buffers commonly coupled to the N number of the memory blocks, afirst program step of sequentially programming, on a page basis, firstto (m−1)^(th) logical pages in each of all the physical pages of firstto (N−1)^(th) memory blocks in response to a first program command, astep of selecting one of the first to (N−1)^(th) memory blocks inresponse to a second program command to obtain a selected memory block,loading data of the first to (m−1)^(th) logical pages stored in a firstphysical page of the selected memory block, and latching the loaded datain first to (m−1)^(th) latches of each of the page buffers, and a secondprogram step of latching new program data, received along with thesecond program command, in an m^(th) latch of the corresponding pagebuffer and programming the data, stored in the first to m^(th) latchesof the page buffer, into a first physical page of the N^(th) memoryblock.

The method further includes a step of resetting all the latches of thepage buffer, loading data of first to (m−1)^(th) logical pages of asecond physical page of the selected memory block, and latching theloaded data in the first to (m−1)^(th) latches of the page buffer,respectively, when receiving a third program command after completingthe second program step, and a third program step of latching newprogram data, received along with the third program command, in them^(th) latch of the page buffer and programming the data, stored in thefirst to m^(th) latches of the page buffer, into a second physical pageof the second memory block.

The first to (N−1)^(th) memory blocks are sequentially selected inresponse to a block address.

The method further includes the step of erasing the first memory block,after programming data of first to (m−1)^(th) logical pages stored inall word lines of the selected memory block into the N^(th) memoryblock.

The method further comprises the step of loading data stored in theselected memory block and memory blocks other than the N^(th) memoryblock, and storing the loaded data, together with new program data, inthe selected memory block, when receiving a fourth program command aftererasing the selected memory block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram showing a nonvolatile memory device according to anembodiment of this disclosure;

FIG. 1B is a diagram showing an embodiment of the page buffer unit ofthe nonvolatile memory device shown in FIG. 1A;

FIG. 2 is a diagram showing distributions of the threshold voltagesaccording to a program operation in a known 3-bit MLC;

FIG. 3A is a flowchart illustrating a portion of a program operationaccording to a first embodiment of this disclosure;

FIG. 3B is a flowchart illustrating another portion of the programoperation according to the first embodiment of this disclosure; and

FIGS. 4A and 4B are diagrams illustrating the sequence of dataprogrammed into memory blocks according to different embodiments of thisdisclosure.

DESCRIPTION OF EMBODIMENTS

Hereinafter, some embodiments of the present disclosure will bedescribed in detail with reference to the accompanying drawings. Thefigures are provided to allow those having ordinary skill in the art tounderstand the scope of the embodiments of the disclosure.

FIG. 1A is a diagram showing a nonvolatile memory device according to anembodiment of this disclosure.

Referring to FIG. 1A, the nonvolatile memory device 100 according to theembodiment of this disclosure includes a memory cell array 110, a pagebuffer unit 120, a Y decoder 130, an X decoder 140, a voltage supplyunit 150, and a control unit 160.

The memory cell array 110 includes a number of memory blocks BK. Thememory blocks each include memory cells each capable of storing 3-bitinformation. Furthermore, the memory cells are coupled together by wordlines WL and bit lines BL.

The page buffer unit 120 includes a number of page buffers PB. Each ofthe page buffers PB are coupled to one or more bit lines and areconfigured to store data to be stored in selected memory cells or toread data stored in selected memory cells and store the read data.

The Y decoder 130 is configured to provide a data IO path to the pagebuffers PB in response to a control signal. The X decoder 140 isconfigured to enable a memory block and to couple the word lines of anenabled memory block with a global word line for supplying operatingvoltages.

The voltage supply unit 150 is configured to generate a high voltage fora program, read, or erase operation. The control unit 160 is configuredto control the operations of the nonvolatile memory device 100.

In particular, the control unit 160 controls an operation for selectingan address of a page in which input data will be programmed according toa program command, and an operation for reading data stored in an LSBpage and a CSB page and programming LSB, CSB, and MSB data into anotherword line at the same time.

FIG. 1B is a diagram showing an embodiment of a page buffer unit of thenonvolatile memory device shown in FIG. 1A.

Referring to FIG. 1B, the memory blocks BK of the memory cell array 110include cell strings coupled to the respective bit lines.

One cell string includes 0^(th) to thirty-first memory cells C0 to C31coupled in series between a drain select transistor DST and a sourceselect transistor SST.

The drains of the drain select transistors are coupled to the respectivebit lines, and the sources of the source select transistors are coupledto a common source line CSL.

The gates of the drain select transistors are coupled to a drainselection line DSL, and the gates of the source select transistors arecoupled to a source selection line SSL. The gates of the 0^(th) tothirty-first memory cells C0 to C31 are respectively coupled to 0^(th)to thirty-first word lines WL0 to WL31.

The 0^(th) to thirty-first memory cells C0 to C31 are MLCs each capableof storing 3-bit information. Accordingly, one word line includeslogical pages, including LSB pages, CSB pages, and MSB pages.

In the embodiment of this disclosure, a pair of an even bit line BLe andan odd bit line BLo is coupled to one page buffer PB. Here, the pagebuffer PB includes a number of latch circuits for storing data. In anembodiment of this disclosure, the nonvolatile memory device includesMLCs each capable of storing 3-bit information, and so three or morelatch circuits have to be included in each page buffer PB.

FIG. 2 is a diagram showing distributions of the threshold voltagesaccording to a program operation in a known 3-bit MLC.

Referring to FIG. 2, in a nonvolatile memory device including MLCs eachcapable of storing 3-bit information, a program operation for threelogical pages is performed on one word line.

That is, as shown in FIG. 2, in the state in which all memory cells arein an erase state, an LSB page program is performed on memory cellsbelonging to one threshold voltage distribution, and so the thresholdvoltage distribution is divided into two distributions.

In the state in which the LSB page program has been performed, when aCSB page program is performed, the two threshold voltage distributionseach are divided into two more threshold voltage distributions,resulting in a total of four threshold voltage distributions. Next, whenan MSB page program is performed, each of the four threshold voltagedistributions are also divided into two more threshold voltagedistributions, resulting in a total of eight threshold voltagedistributions.

Here, while the three logical page programs, including the LSB, CSB, andMSB pages, are performed, memory cells neighboring selected memory cellsare continuously influenced by the program operations, and the selectedmemory cells are also influenced by each other.

To prevent interference among neighboring memory cells during the threelocal page programs, a method of latching data to be stored in the LSB,CSB, and MSB pages in the page buffer PB at a time and performing theLSB, CSB, and MSB page programs at the same time can be used. However,performing the three logical page programs at the same time can have aneffect on neighboring memory cells.

Accordingly, in an embodiment of this disclosure, in the case of an MLCcapable of storing 3-bit information, only up to two logical pages forall the word lines of a memory block can be programmed at the same time,in order to reduce such interference. In the case in which the MSB pagehas to be programmed, a method of reading data already stored in the LSBand CSB pages, combining the read data and data to be programmed intothe MSB page, and programming the combined data into another memoryblock can be used.

FIG. 3A is a flowchart illustrating a portion of a program operationaccording to a first embodiment of this disclosure.

To describe FIG. 3A, reference will be made to FIGS. 1A and 1B, and itis assumed that all the memory cells of the memory cell array 110 are inan erase state.

Referring to FIG. 3A, when a program command and program data areinputted at step S301, the control unit 160 selects the 0^(th) word lineWL<0> of the 0^(th) memory block BK<0> at step S303 and programs theprogram data into an LSB page at step S305. Next, when a program commandand program data are inputted at step S307, the control unit 160 selectsthe 0 ^(th) word line WL<0> of the 0^(th) memory block BK<0> andprograms the program data into a CSB page at step S309.

Next, when a program command and program data are inputted at step S311,the control unit 160 determines whether there exists, in the 0^(th)memory block BK<0>, a word line that will be programmed at step S313. Inother words, the control unit 160 determines whether the LSB and CSBpage programs have been performed up to the thirty-first word lineWL<31> (i.e., the last word line).

If, as a result of the determination, the LSB and CSB page programs aredetermined not to have been performed up to the thirty-first word lineWL<31>, the control unit 160 increases an address of a word line to beselected (i.e., selects the next word line by, for example, increasingthe address/number 30 to the address/number 31 in order to go fromselecting the thirtieth word line WL<30> to selecting the thirty-firstword line WL<31>) and performs only the LSB and CSB page programsaccording to a program command and program data at steps S315 to S321.

To this end, when selecting addresses to indicate word lines to beprogrammed in response to the program command, the control unit 160performs only the LSB and CSB page programs on all the word lines of the0^(th) memory block BK<0>.

After the LSB and CSB page programs are all performed on the 0^(th) tothirty-first word lines WL<0> to WL<31> of the 0^(th) memory blockBK<0>, the process turns to step S341. In other words, if at step S313it is determined that the LSB and CSB page programs have been performedup to the last word line (e.g., WL<31>), then the process continues tostep S341. The control unit 160 then performs a subsequent process, suchas that shown in FIG. 3B.

FIG. 3B is a flowchart illustrating another portion of the programoperation according to the first embodiment of this disclosure, which isperformed subsequently to the portion of the program operation of FIG.3A.

Referring to FIG. 3B, if, as a result of the determination at step S313,the LSB and CSB page programs are determined to have been performed upto the thirty-first word line WL<31> (i.e., up to the last word line),the control unit 160 loads the data of the LSB and CSB pages, stored inthe 0^(th) word line WL<0> of the 0^(th) memory block BK<0>, and storesthe loaded data in the two latch circuits of the page buffer PB at stepS341. Here, program commands and program data are stored in one of thelatch circuits of the page buffer PB other than the two latch circuits.To this end, as described above, the page buffer PB has to include threeor more latch circuits, and LSB, CSB, and MSB data are stored in therespective latch circuits.

In the state in which, as described above, the three bit data are allstored in the page buffer PB, at step S343 the control unit 160 programsthe three bit data into the 0^(th) word line WL<0> of the first memoryblock BK<1> at the same time. Accordingly, the threshold voltages ofmemory cells coupled to the 0^(th) word line WL<0> of the first memoryblock BK<1> are classified into eight threshold voltage distributions.

Next, when a program command and program data are inputted at step S345,the LSB and CSB data stored in the 0^(th) word line WL<0> to thethirty-first word line WL<31> of the 0^(th) memory block BK<0> are movedto the word lines of the first memory block BK<1>. At step S347, it isdetermined whether the program has been performed for each of the wordlines of the first memory block BK<1>, such that each memory cell hasthree bits. If, at step S347, it is determined that not all of the wordlines of the first memory block BK<1> have been programmed, then theprocess proceeds to step S349. At step S349 the control unit 160 loadsthe data of the LSB and CSB pages, stored in the next word line of the0^(th) memory block (e.g. the first word line WL<1>). After step S349,the process proceeds to step S351 where the control unit 160 programsthe three bit data into the next word line (e.g., the first word lineWL<1>) of the first memory block BK<1>. The above processes S345 to S351are then repeatedly performed until all of the word lines (e.g., the0^(th) word line WL<0> to the thirty-first word line WL<31>) of thefirst memory block BK<1> are programmed with the three bit data.

After the LSB and CSB data stored in the thirty-first word line WL<31>of the 0^(th) memory block BK<0> are loaded and then programmed into thethirty-first word line WL<31> of the first memory block BK<1> along withMSB data, the 0^(th) memory block BK<0> is erased, such that it can beused for other programs. In other words, after it has been determined atstep S347 that the program has been performed up to the last word line,the process proceeds to step S353 where the 0^(th) memory block BK<0> iserased.

As three bits are programmed at a time, as described above, interferenceon neighboring cells can be reduced, and the memory cell array 110 canbe programmed like a 2-bit MLC having only LSB and CSB pages. If data of3 bits or more are to be programmed, a method of programming the data of3 bits at a time is used.

FIGS. 4A and 4B are diagrams illustrating the sequence of dataprogrammed into memory blocks according to different embodiments of thisdisclosure.

In FIGS. 4A and 4B, it is assumed that the memory cell array 110includes only 0^(th) to third memory blocks BK<0> to BK<3> and thesequence is assigned to program data.

Referring to FIG. 4A, the LSB and CSB page programs have been performedfor the first and second memory blocks BK<1> and BK<2>. In the case inwhich further program data exist, the data stored in the LSB and CSBpages of the 0^(th) memory block BK<0> can be loaded and then stored inthe third memory block BK<3>. As shown in FIG. 4A, the MSB pages of the0^(th) to second memory blocks BK<0> to BK<2> are empty. Accordingly,the data stored in the 0^(th) memory block BK<0> are loaded and thenstored in the third memory block BK<3> along with the further programdata.

When the third memory block BK<3> is fully programmed, the 0^(th) memoryblock BK<0> is erased, and data stored in the first memory block BK<1>are loaded and then stored in the 0^(th) memory block BK<0>.

An alternative method is described below with reference to FIG. 4B.

That is, as described above with reference to FIGS. 3A and 3B, when LSBand CSB page programs are performed on all the word lines of the 0^(th)memory block

BK<0>, data stored in the LSB and CSB pages of the 0^(th) memory blockBK<0> are loaded and, together with MSB data, and programmed into thefirst memory block BK<1> in response to a subsequent program command.The 0^(th) memory block BK<0> is then erased.

Next, when program data are inputted, the program data are programmedinto only the LSB and CSB pages of the 0^(th) memory block BK<0> or anyone of the second to third memory blocks BK<2> to BK<3>. Next, the datastored in the LSB and CSB pages of the corresponding memory block aremoved to another memory block.

In this case, an operation for arbitrarily selecting a memory block inwhich two pages are programmed, programming data into the LSB and CSBpages of the corresponding memory block, and moving the data of the LSBand CSB pages to another memory block may be repeatedly performed.However, if only a specific memory block is used, program/erase cyclesfor the specific memory block are increased, and so the specific memoryblock can be deteriorated. To avoid this problem, an arbitrary memoryblock can be properly selected and programmed.

According to the above program method, data of 3 bits or more can bestored in the memory cell array 110, including memory cells each capableof storing 3 bits, while programming the memory cell array 110 like a2-bit MLC to a maximum.

Accordingly, the memory cell array according to the present disclosurehas the same memory capacity as one for storing 3-bit information, butoperates like a 2-bit MLC. Consequently, an interference phenomenon canbe reduced, and reliability of data can be improved.

Further, in the program method of this disclosure, in the state in whichCSB data are not stored, only LSB data stored in memory cells can beloaded and programmed along with MSB data. In this case, the CSB datacan be masked as dummy data.

As described above, in accordance with the method of programming anonvolatile memory device according to the present disclosure, when anMLC capable of storing N bits (where N is a positive integer) isprogrammed, up to only N-1 bits are first programmed into all the wordlines of a memory block. Accordingly, an interference phenomenon can bereduced. Furthermore, before an N^(th) bit is programmed, 1 to N-1 bitdata are previously loaded, and the N bits are programmed into the wordlines of another memory block at the same time. Accordingly, aninterference phenomenon can be minimized.

1-9. (canceled)
 10. A programming method of a non-volatile memorydevice, comprising: storing LSB data and CSB data in an LSB page and aCSB page of word lines included in a first memory block; receiving aprogram command and MSB data; and storing the LSB data read from the LSBpage, the CSB data read from the CSB page, and the MSB data in a secondmemory block.
 11. The programming method of claim 10, wherein first LSBdata and first CSB data are stored in a first LSB page and a first CSBpage of a word line selected from the first memory block and second LSBdata and second CSB data are then stored in a second LSB page and asecond CSB page of a next word line.
 12. The programming method of claim10, wherein the LSB data, the CSB data, and the MSB data are receivedalong with different program commands.
 13. The programming method ofclaim 10, further comprising reading the LSB data and the CSB datastored in the LSB page and the CSB page of the first memory block, afterreceiving the MSB data.
 14. The programming method of claim 10, whereinthe LSB data, the CSB data, and the MSB data are simultaneously storedin an LSB page, a CSB page, and an MSB page of word lines included inthe second memory block.
 15. The programming method of claim 10, furthercomprising erasing the LSB data and the CSB data stored in the firstmemory block, after storing the LSB data, the CSB data, and the MSB datain the second memory block.
 16. A programming method of a non-volatilememory device, comprising: storing data in first to (n−1)^(th) logicalpages of n logical pages of word lines included in a first memory block;receiving a program command and MSB data; and storing the data read fromthe first to (n−1)^(th) logical pages and the MSB data in n logicalpages of word lines included in a second memory block.
 17. Theprogramming method of claim 16, wherein first data is stored in first to(n−1)^(th) logical pages of a word line selected from the first memoryblock and second data is then stored in first to (n−1)^(th) logicalpages of a next word line.
 18. The programming method of claim 16,wherein the data stored in the first to (n−1)^(th) logical pages and theMSB data are received along with different program commands.
 19. Theprogramming method of claim 16, further comprising reading the datastored in the first to (n−1)^(th) logical pages of the first memoryblock, after receiving the MSB data.
 20. The programming method of claim16, wherein the data read from the first to (n−1)^(th) logical pages andthe MSB data are simultaneously stored in the n logical pages of theword lines included in the second memory block.
 21. The programmingmethod of claim 16, further comprising erasing the data stored in thefirst memory block, after storing the data read from the first to(n−1)^(th) logical pages and the MSB data in the second memory block.22. A non-volatile memory device, comprising: a memory cell arrayconfigured to include a first memory block and a second memory block;and circuits configured to store data in first to (n−1)^(th) logicalpages of n logical pages of word lines included in the first memoryblock and store MSB data, received along with a program command, in thesecond memory block along with the data read from the first to(n−1)^(th) logical pages.
 23. The non-volatile memory device of claim22, wherein the circuits are configured to store first data first to(n−1)^(th) logical pages of a word line selected from the first memoryblock and then store second data in first to (n−1)^(th) logical pages ofa next word line.
 24. The non-volatile memory device of claim 22,wherein the circuits are configured to read the data stored in the firstto (n−1)^(th) logical pages of the first memory block, after receivingthe MSB data.
 25. The non-volatile memory device of claim 22, whereinthe circuits are configured to simultaneously store the data read fromthe first to (n−1)^(th) logical pages and the MSB data in n logicalpages of word lines included in the second memory block.
 26. Thenon-volatile memory device of claim 22, wherein the circuits areconfigured to erase the data stored in the first memory block, afterstoring the data read from the first to (n−1)^(th) logical pages and theMSB data in the second memory block.
 27. The non-volatile memory deviceof claim 22, wherein the circuits are configured to store the data readfrom the first to (n−1)^(t) logical pages of the first memory block infirst to (n−1)^(th) logical pages of word lines included in the secondmemory block and store the MSB data in n^(th) logical pages of the wordlines of the second memory block.